The invention relates to a circuit arrangement with at least one input and at least one output for forwarding an input signal that can be parallelized and digitized.
Circuit arrangements of this type are employed for example for a coupling network component of a network node in a packet-switching data network.
An N-to-N knockout switching node for a high-performance packet-switching system is described in U.S. Pat. No. 4,760,570. This is likewise described by the authors Y. S. Yeh, M. G. Hluchyj and A. S. Acampora in the IEEE Journal on Selected Areas in Communication, Volume SAC-5, No. 5, 1987, on pages 801-808 in an article entitled "The Knockout Switch: A Simple Modular Architecture for High-Performance Packet Switching" as a circuit arrangement which is composed of a plurality of inputs and a plurality of outputs, and which is provided for a filterable forwarding of a serial data packet from one of the inputs to an output that can be determined from the data packet. Data packets are filtered out by means of a filter connected directly downstream of the input. These data packets that can be input serially at the input are forwarded serially in a concentrator. The concentrator is here a matrix-shaped permutation circuit composed of basic elements, from which the data packet is forwarded serially bit by bit. The data packets are forwarded serially from the concentrator into a shifter. A serial routing and serial forwarding for a temporary storage in packet memories, into which the data packets are serially read simultaneously from case to case and serially read out again, is carried out for the serial data packet stream by means of the shifter. A common buffer composed of shifters and a specific number of packet memories is provided for each of the outputs. The serial data packet stream from a comparatively large number of inputs can be concentrated and stored in a buffer assigned to the output via a plurality of concentrators with upstream filters by means of an interconnection provided for each of the outputs. The routing of the data packet stream is carried out decentrally and locally. The relevant output for forwarding the data packet is determined from the data packet in the filters. All the data packets that are not destined for the output assigned to the filter are extracted by means of the filter. Except for the storage in the packet memory, the data packets are otherwise always forwarded serially. This so-called KO switch is free of internal blockages since the path of the serial data packet from the input to the output is not correlated with the path of other serial data packets to other outputs. Depending on the number of packet memories per output, external blockages can be prevented. Data packets that arrive simultaneously at a plurality of inputs and are destined for the same output can be temporarily stored in the packet memories of the buffer.
The authors Thomas A., Coudreuse J.-P. and Servel M. describe in an article entitled "Asynchronous Time-Division Techniques: An Experimental Packet Network Integrating Videocommunication" at the Symposium ISS '84 Florence, Italy, 7th to 11th May 1984, Session 32 C Paper 2, a switching node which is called "Prelude". Given an external bit rate of 280 megabits per second on the input and output lines and with 35 megabits per second internally, low loss rates and delays can be achieved even with a high load. Control and storage are carried out centrally. The 16-byte long packets arriving on the 16 input lines of the node are synchronized and are read into the central packet buffer byte by byte offset by one byte in each case. This technique is also termed "paragonal", which is derived from parallel-diagonal. The central control unit performs the translation of the virtual connection addresses and initiates the entry, at which the respective packet is located in the central packet buffer. The entry is made in a queue assigned to the corresponding output, this queue being processed in the order of entry. The paragonal structure of the preprocessing of the data packets relieves the load on the central control unit.
European Patent Application EU-0263418-A2 discloses a switching network for switching digital input signals which arrive on input lines to digital output signals which are output on output lines, so that the input signals are synchronized and combined block by block in time slots, and also that a multiplex signal is obtained which is combined into multiplex blocks block by block from the input signals synchronized in time slots, and also that the multiplex blocks of the multiplex signal can be exchanged with one another for forming a switched-through multiplex signal, and also that the multiplex blocks of the switched-through multiplex signal are converted and are output block by block as output signals. A switching control signal, a so-called connection control signal, is required, by means of which it is defined which of the input lines is to be switched through to which of the output lines in time slots, so that the exchange of the multiplex blocks is controlled by this switching control signal.